Analysis and VLSI Architecture of High Definition and Scalable Videocoding Standards

This book addresses the algorithm analysis and VLSI architecture of video encoders, especially for high definition and scalable video coder. The three design challenges and related system issues of memory bandwidth (including system memory and internal memory), hardware area, and power consumption (required operating frequency) are all discussed. With the high definition encoder, the authors focus on algorithm modification and design parallelism to provide high processing capability for the video encoder. Several corresponding hardware schedules are also included to cooperate with proposed architecture. For scalable video coding, the emphasis is placed not only on video algorithms, but also on hardware performance. The algorithm modification, data reuse schemes from frame-level to candidates-level, and architecture design contribute in the developing of three scalabilities and first MCTF hardware design. Finally, the first SVC encoder chip for HDTV1080p is presented and all above design issues are considered together.