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This title introduces a comprehensive approach to timing, power, and communication analysis of embedded software processes. Embedded software timing, power and communication are typically not unique but occur in intervals which result from data dependent behaviour, environment timing and target system properties. In system design, these intervals are used in many ways. In some cases, only the worst case is of interest, for example, for single processor schedulability analysis, whereas in another context both best and worst cases are relevant, such as for multiprocessor scheduling. In all these cases, these behavioural intervals of the individual software processes are fundamental data needed to analyze system behaviour. With growing importance of embedded software, formal analysis of behavioural intervals has met increasing interest. While all approaches are conservative, that is, all possible timing behaviour (or communication, power consumption) is included in the resulting intervals, the main differences are in the architecture features that are covered by the hardware model and the width of the conservative interval. The closer this interval to the real timing bounds, the higher is the practical use of formal analysis. Analysis techniques leverage on previous work in compiler technology by using basic blocks as elementary units for architecture modelling and path analysis. The work presented here offers an alternative direction, moving from basic block-based analysis to an analysis based on larger program segments with a single execution path.
