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Random number generators are used in many areas of engineering, computer science, most notably in simulations and cryptographic applications. Only a true random number generator is secure because the output bits are non-repeating and non-reproducible. A true random number generator on a field programmable gate array allows the generator on chip reducing the possibility of a breach in security. An oscillator sampling technique is an effective TRNG in a Xilinx FPGA. This research examines how the differences in period of the oscillators, the size of the jitter zone, and sampling on the rising and falling edge of the oscillator rather than just the rising edge affects the TRNG. The proportion of the size of the jitter zone compared to the period difference between the two oscillators limits the performance. As the jitter zone gets larger, the proportion of the jitter zone to the difference in periods of the oscillators must increase for the output to remain random. Sampling on the rising and falling edge instead of only the rising was not effective. The output was random for only a jitter zone of 24 ps with a period difference of 50 ps and 100 ps.
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