Digital Timing Macromodeling for VLSI Design Verification

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A history of the development of simulation techniques, presenting a detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level and gate-level simulation. The text also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 examines the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodelling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address topics such as: the device model detail; transistor coupling capacitance; effective channel length modulation; series transistor reduction; effective transconductance; input terminal dependence; gate parasitic capacitance; the body effect; the impact of parasitic RC-interconnects; and the effect of transmission gates.