Embedded Systems and Software Validation

7 ½ X 9 ¼ in 1 Introduction

2 Model Validation
2.1 Platform vs Syst em Behavior
2.2 Criteria for Design Model 2.3 Informal Requiremen ts: A Case Study
2.3.1 The Requirements Document 2.3.2 Simplicati on of the Informal Requirements 2.4 Common Modeling Notations 2.4. 1 Finite State Machines (FSM) 2.4.2 Communicating FSMs 2.4.3 Messa ge Sequence Chart based Models
2.5 Remarks about Modeling Notations< BR>2.6 Model Simulations 2.6.1 FSM simulations 2.6.2 Simulating MS C-based System Models 2.7 Model-based Testing 2.8 Model Checking2.8.1 Property Specifcation 2.8.2 Checking procedure 2.9 The SPI N Validation Tool 2.10 The SMV Validation Tool 2.11 Case Study: Ai r Traffic Controller 2.12 References 2.13 Exercises

3 Co mmunication Validation 3.1 Common Incompatibilities
3.1.1 Sending /receiving signals in di erent order 3.1.2 Handling a diffrent signal alphabet 3.1.3 Mismatch in data format 3.1.4 Mismatch in data rat es 3.2 Converter Synthesis
3.2.1 Representing Native Protocols an d Converters 3.2.2 Basic ideas for Converter synthesis 3.2.3 Vario