The continuing growth in the size and complexity of VLSI devices requires a parallel development of well-designed, efficient CAD tools. Such tools must be available for the whole design cycle - synthesis and functional verification, testability analysis, test generation and fault coverage and layout. The majority of commercially available tools are based on an algorithmic approach to the problem and there is a continuing research effort aimed at improving existing tools of this form and developing new algorithms. The sheer complexity of the problem has, however, led to an interest in examining the applicability of expert systems and other knowledge based techniques to certain problems in the area and a number of results are becoming available. The aim of this book, which is based on material given at an IEE Colloquium of the same name, is to sample the present state-of-the-art in CAD for VLSI. It covers both newly developed algorithms and applications of techniques from the artificial intelligence community. The editors believe it will prove of interest to all engineers concerned with design and testing of integrated circuits and systems. Although it is not intended as a course text, many of the chapters will provide background reading for postgraduate and final year undergraduate students following courses in VLSI design. Chapters are arranged in three groups covering topics in synthesis, test and testability and layout.